1. Field of the Invention
One embodiment of the invention disclosed in this specification relates to a semiconductor device, a method for driving a semiconductor device, or a method for manufacturing a semiconductor device.
2. Description of the Related Art
Semiconductor elements in signal processing circuits such as central processing units (CPUs) have been downsized to increase operation speed and integration degree, and now transistors with a channel length of approximately 30 nm are manufactured. On the other hand, downsizing semiconductor elements leads to an increase in power consumption (leakage power) due to leakage current of transistors in CPUs. Specifically, most of the power consumption of conventional CPUs has been power consumed at the time of arithmetic operations (operating power), while leakage power accounts for at least 10% of the power consumption of CPUs in recent years.
The number of CPU cores in existing processors is significantly increased to improve computational performance and efficiency. However, when leakage power is increased as above in multi-core systems and many-core systems, power is consumed also in an unused CPU core; thus, it is difficult to construct a system with high power efficiency. In order to reduce power consumed in an unused CPU core, there has been suggested a method of stopping the supply of power with the use of a state retention register (i.e., power gating or normally-off computing). Specifically, a technique combined with a nonvolatile state retention register attracts attention (Non-Patent Document 1).
In a normally-off computer, the supply of power is stopped at short intervals, so that a memory element used for a state retention register needs to operate at high speed. For example, flash memory, which is nonvolatile memory, does not fill the need for high-speed performance, and its write cycles are inadequate for use as a state retention register.
In view of the above, there has been suggested a memory device in which a nonvolatile memory element that can operate at higher speed and has a larger number of write cycles than flash memory is provided in addition to a volatile memory element (Patent Document 1).
Patent Document 1 discloses an electronic circuit that includes a volatile data retention circuit using an inverter and a ferroelectric capacitor and can hold data by storing the data in the ferroelectric capacitor even when the supply of power is stopped.